The present invention relates to memories, systems using memories, and methods for accessing memories.
To increase throughput of memory access operations, some data processing systems employ multi-ported memories. Multiple access operations are allowed to proceed in parallel through different ports to increase the throughput. However, the cost of memories increases with the number of ports. Therefore, it is desirable to use memories having fewer ports while still obtaining high throughput. Further, in memory systems with multi-ported memories, separate address and data buses are used for each port. It is desirable to reduce the number of address and data buses in the memory system.
It is also desirable to increase the address and data bus utilization in memories that use different timing for read and write operations. Such memories include fast synchronous SRAMs (static random access memories). Different timing for read and write operations causes address or data bus utilization penalty when the memory is switched from a write operation to a read operation or from a read to a write. It is desirable to reduce or eliminate such penalty.
It is also desirable to provide memory systems that enable one to obtain a non-blocking ATM (asynchronous transfer mode) switch, or some other switch, by combining two or more switch fabrics to increase the number of ports but without increasing the cost per port.